GaN devices can switch with edge rates that expose parasitic elements a slower silicon design may tolerate. The schematic may be correct while a few millimeters of shared copper create overshoot, ringing, false turn-on, or unexpected loss. Layout therefore begins with current loops, not with component outlines or convenient routing channels.
Identify three different loops
The high-frequency power loop includes the local bus capacitor, high-side device, low-side device, and the connections between them. The gate loop runs from the driver output through the gate and back to the driver’s source reference. Common-source inductance is the portion shared by the gate return and the main power current. It produces feedback that changes the effective gate voltage during fast current transitions.
Mark these loops on the schematic before placement. The smallest-looking board is not automatically the lowest-inductance board; current must have a close, continuous return path on an adjacent layer.
Place in the order of edge rate
- Place the high-frequency ceramic bus capacitors directly across the half-bridge supply terminals.
- Place the two power devices to minimize the commutation path.
- Place the driver, gate resistors, and driver bypass capacitor against the device control pins.
- Connect the driver return to the source or Kelvin-source reference without sharing the power path.
- Route slower PWM, sensing, and housekeeping nets after the switching geometry is fixed.
Wide copper helps resistance and spreading, but loop inductance also depends strongly on length and the spacing between outgoing and return conductors. Broad overlapping planes on adjacent layers can create a low-inductance path. However, overlap under the switch node can add capacitance to ground or other quiet nets, increasing common-mode current and switching loss.
Control the switch node
Keep the switch-node area no larger than required for current and thermal performance. Do not route sensitive signals beneath or beside it. Provide a clear keep-out for feedback, current-sense, communication, and connector traces. If a heatsink or chassis is near the switch node, include the resulting capacitance in common-mode noise analysis.
Thermal vias and internal copper can reduce temperature, but they must not accidentally enlarge the high-dv/dt structure. Follow the device’s recommended land pattern and consider a dedicated thermal path tied to a quiet potential when the package architecture allows it.
Prototype for measurement access
Add low-inductance probe points for gate-to-source voltage and the local bus. Avoid long test loops that become part of the circuit during measurement. Use a high-bandwidth differential probe for the switch node and a current measurement method with adequate rise time. Compare overshoot and ringing across bus voltage, load current, dead time, and temperature.
- Check that the driver bypass voltage remains stable during each edge.
- Confirm the off-state gate stays below its turn-on threshold with margin.
- Measure thermal performance after electrical loop optimization.
- Repeat the test with production connectors, cables, and enclosure.
When GaN performance falls short of the datasheet promise, the first diagnostic should be the physical current path. A disciplined placement sequence often improves efficiency, voltage margin, and EMI simultaneously.
Technical reference: Texas Instruments, Layout Considerations for a GaN Power Stage.
