How to Tune a MOSFET Gate Resistor for Efficiency and EMI
A measurement-led method for choosing gate resistance without trading away more efficiency, voltage margin, or EMI performance than necessary.
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Technical guidance, application perspectives and reliability practices for power semiconductor design.
A measurement-led method for choosing gate resistance without trading away more efficiency, voltage margin, or EMI performance than necessary.
Turn package loss into a realistic junction-temperature estimate by designing and validating copper spreading, vias, interfaces, and airflow together.
Use output charge and effective capacitance—not one small-signal Coss value—to assess dead time and zero-voltage switching in an LLC stage.
Why a MOSFET that survives one unclamped inductive event may still need substantial derating for repetitive avalanche operation.
Reduce body-diode loss without creating reverse current or shoot-through by tuning synchronous-rectifier timing across the full operating range.